Senior FPGA Engineer

Job Function
Port ASIC RTL code to FPGA environment. Write scripts for synthesis and
Place And Route (PAR) to automate and optimize the FPGA build performance
Collaborate with ASIC designers to debug and resolve RTL issues. Verify FPGA
build, and support design verification

Requires a strong digital design background. Experience with large FPGAs.
Must have practical experience with details of RTL development
(Verilog/System Verilog and/or VHDL) . Must have good familiarity with
latest FPGA tools, including: Synplify Pro/Premier, Identify, Xilinx Tool
suite, Altera Tool suite. Knowledge of Eve Tool is a plus. Must be familiar
with RTL simulation/verification environments and tools. Familiarity with
software development environments would also be an advantage.

Additional requirements: Ability to work in a team environment. Good
self-direction and time management skills. Willing to travel to other
countries to support customers on site.

Work and define hardware platform for future emulation. Work with
architecture/microarchitecture/RTL Design team to implement the design in
FPGA. Work with verification team to debug errors. Work with SW Tool
Development team to verify that new SW tool flows/environments supports new

Education Requirements
A bachelors degree in computer or electrical engineering is a minimum

If interested please send an email to, please use
the code "DD" in your email subject.