SA,
a digital designer engineer opening at CWS (center of wireless studies)

Position: Design Engineer

Work in design and implementation of digital communications transceivers. Fully simulate the system in Matlab and/or C++, then convert the system model into a synthesizable RTL code.

Position requirements:

1.Strong background in Digital Communications.

2.Work independently and be self motivated.

3.proficient in Matlab

4.proficient in Verilog (VHDL knowledge is acceptable, but you will have to learn Verilog)

5.Knowledge of C++ is preferred

6.Must be graduated from cairo or 3ainshams uni.

7.Must be in Master

If interested, please email your CV to (mahmoudabdelall2005 @yahoo.com )